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pbl 3798, pbl 3798/2 subscriber line interface circuit description pbl 3798 is an analog subscriber line interface circuit (slic), which is fabricated in a 75 v bipolar, monolithic process. the programmable, constant current feed circuit incorporates a switch mode regulator to minimize on-chip power dissipation. a stand-by state further reduces idle power dissipation, while allowing the supervisory functions to be active. tip-ring polarity is reversible without altering slic supervisory and voice frequency (vf) functions. tip and ring outputs can be set to high impedance states. these and other operating states are activated via a parallel, four bit control word. an external resistor controls the off-hook detector threshold current. a ground key detector with internal reference reports tip/ring dc current unbalance. the ring trip detector can operate with both balanced and unbalanced ringing systems. the three detectors are read via a shared output. ring and test relay drivers with internal clamp diodes are provided. the complex or real two-wire impedance is set by a scaled, lumped element network. two- to four-wire and four- to two-wire signal conversion is provided by the slic in conjunction with either a conventional or a programmable codec/filter. longitudinal line voltages are suppressed by a control loop within the slic. the pbl 3798 package is 28-pin, dual-in-line; 32-pin or 44-pin j-leaded chip carrier. the difference between pbl 3798 and pbl 3798/2 is mainly the longitudinal balance spec. figure 1. block diagram. key features ? on-chip switch mode regulator to minimize power dissipation ? programmable, constant current feed ? line feed characteristics independent of battery variations ? tip-ring polarity reversal function ? tip and ring open circuit state; tip open with ring active state ? detectors: - programmable loop current/ring ground detector - ground key detector - ring trip detector ? ring and test relay drivers ? line terminating impedance, complex or real, set by a simple external network ? hybrid function with conventional or programmable codec/filters ? 70 db longitudinal to metallic balance ? 79 ma peak longitudinal current suppression ? idle noise < 7 dbrnc; <-83 dbup march 1997 input decoder and control loop/gnd key detector vf signal transmission line feed controller and longitudinal suppression two-wire interface ring relay driver test relay driver ring trip comparator 6/4 7/5 40/26 38/25 42/27 34/22 35/23 43/28 3/2 10/7 2/1 ringrly testrly dr dt tipx hpt hpr ringx gnd2 vbat vreg 4/3 31/20 vcc vee 23/16 21/14 22/15 16/11 19/ 20/13 37/24 32/21 29/19 26/17 27/18 c1 c2 c3 c4 e0 det rd vtx rsn rdc gnd1 15/ rsg 8/6 l switching regulator 12/9 11/8 14/10 chs vqbat chclk 17/12 e1 pbl 3798 pbl 3798/5 pbl 3798 pbl 3798 4-127
4-128 pbl 3798 absolute maximum ratings parameter symbol min max unit temperature and humidity storage temperature range t stg -55 +150 c operating ambient temperature range t amb -40 +85 c operating junction temperature range (note 1) t j -40 +135 c power supply v cc with respect to ground v cc -0.4 +6.5 v v ee with respect to ground v ee -6.5 +0.4 v v bat with respect to ground v bat -70 +0.4 v power dissipation continuous power dissipation at t amb = 70 c (note 3) 28-pin, plastic dual-in-line package (n) 1.5 w 44-pin, j-leaded chip carrier (qn) 1.5 w 32-pin, j-leaded chip carrier (rn) 1.7 w ground voltage between gnd1 and gnd2 (note 4) -0.1 +0.1 v switch mode regulator peak current through regulator switch (pin l) i lpk 150 ma regulator switch output (pin l) peak off-state voltage v lpk +2 v relay drivers test relay supply voltage v trly v bat v cc v ring relay supply voltage v rrly v bat v cc v test relay current i trly 80 ma ring relay current i rrly 80 ma ring trip comparator input voltage v dt , v dr v bat 0v input current, t p = 10 ms i dt , i dr -2 +2 ma digital inputs, outputs c1 - c4, e0, e1, det, chclk input voltage v id -0.4 v cc v output voltage (det not active) v od -0.3 v cc v output current i od 3ma tipx and ringx terminals tipx or ringx continuous voltage (notes 5, 6) v t , v r -70 1 v tipx or ringx, pulsed voltage, t w < 10 ms and t rep > 10 s (notes 5, 6) v t , v r -70 5 v tipx or ringx, pulsed voltage, t w < 1 m s and t rep > 10 s (notes 5, 6) v t , v r -90 10 v tipx or ringx, pulsed voltage, t w < 250 ns and t rep > 10 s (notes 5, 6, 7) v t , v r -120 15 v tipx or ringx current i ldc -105 105 ma recommended operating conditions parameter symbol min max unit ambient temperature t amb 070 c case temperature t case 090 c v cc with respect to ground v cc 4.75 5.25 v v ee with respect to ground v ee -5.25 -4.75 v v bat with respect to ground (notes 8, 9, 11) v bat -58 -40 v gnd2 with respect to gnd1 (note 10) v g12 00 v
4-129 pbl 3798 notes 1. the circuit includes thermal protection. refer to section over-temperature protection. operation above 135 c may degrade device reliability. 2. C 3. values apply for junction temperature of 120 c without heatsink. 4. the gnd1 and gnd2 pins should be connected together via a direct printed circuit board trace. 5. v t and v r are referenced to ground. t w is pulse width of a rectangular test pulse and t rep is pulse repetition rate. 6. these voltage ratings require a diode to be installed in series with the vbat pin as shown in figure 12 (d 7 ). 7. r f1 , r f2 3 20 w is also required. pulse supplied to tip and ring outside r f1 , r f2 . 8. for long loop applications with -63 v < v bat < -56 v, the saturation guard reference voltage, v sgref , should be adjusted by calculating a value for resistor r sg as described in the text. note that the adjustment terminal, rsg, is available only on the 44-pin leaded chip carrier package. 9. v bat should be applied with a ? v bat / ? t < 4 v/ m sec. a time constant of 2.6 m s is suggested (e.g. 5.6 w and 0.47 m f). the vbat terminal must at all times be at a lower potential than any other terminal to maintain proper junction isolation. refer to sect ion power-up sequence. 10. gnd1 and gnd2 must be connected before supply voltages. 11. a v bat of maximum -40 v may be used. however with a v bat of -40 to -46 v, the performance on long lines will degrade outside the specified limits. parameters affected are; line current, longitudinal balance, idel channel noise an v bat psrr. long lines is in this case outside the constant current range with the v bat dependant saturation guard activated. figure 2. overload level. 1/ w c << r l , r l = 600 ohm, r t = 60 kohms, r rx = 30 kohms. pbl 3798 tipx ringx rsn vtx r t r rx e rx r l v tro i ldc c e l v txo (e l = 0) + + (e rx = 0) 42/27 32/21 43/28 29/19 electrical characteristics 0 c t amb 70 c, v cc = +5 v 5%, v ee = -5v 5%, -58 v v bat -46 v, gnd1 = gnd2, z tr (2-wire ac terminating impedance) = 600 w , z l (line impedance) = 600 w , r f1 = r f2 = 0 w , r t = 60 k w , r rx = 30 k w , r dc1 = r dc2 = 3.125 k w , r sg = , r d = 51.1 k w , r ch = 910 w , r bat = 10 w , c hp = 0.33 m f, c dc = 0.47 m f, c d = 0.01 m f, c tc = c rc = 2200 pf, c ch1 = 0.047 m f, c ch2 = 1500pf, c flt = 0.47 m f, c bat = 0.47 m f, c q = 0.33 m f, l = 1mh, unless otherwise specified. the specifications are with respect to exact external component values. terminal number reference pin x/y denotes 44-pin (x) and 28-pin (y) package terminal number respectively. ref parameter fig conditions min typ max unit 2-wire port overload level, v tro 2 1% thd, e l = 0, f = 1 khz, 3.1 3.5 v pk (note 1) 9.0 10.1 dbm 9.0 10.1 dbu input impedance, z trx note 3 longitudinal impedance, z lot , z lor 3f 100 hz 25 40 w /wire longitudinal current limit, i lot , i lor f 100 hz active state 20 28 ma rms /wire stand-by state 8.5 19 ma rms /wire longitudinal to metallic balance, b lm ieee standard 455-1985 0.2khz < f < 3.4khz, note 4 standard version normal polarity 50 70 db reversed polarity 50 65 db -/2 version normal polarity 60 70 db reversed polarity 55 65 db average per lot, norm. polarity 65 db
4-130 pbl 3798 metallic to longitudinal balance, b ml fcc part 68 paragraph 68.310 0.2khz < f < 4.0khz 40 db f = 1.0khz 53 db longitudinal to metallic balance, b lme 4 0.2khz < f < 3.4khz , e lo b lme = 20 ? log v tr standard version normal polarity 50 70 db reversed polarity 50 65 db -/2 version normal polarity 60 70 db reversed polarity 55 65 db longitudinal to four wire balance, b lfe 4 0.2khz < f < 3.4khz e lo b lfe = 20 ? log v tx standard version normal polarity 50 70 db reversed polarity 50 65 db -/2 version normal polarity 60 70 db reversed polarity 55 65 db metallic to longitudinal balance, b mle 5e tr b mle = 20 ? log , e rx = 0 v lo 0.2khz < f < 4.0khz 40 db f = 1.0 khz 53 db four wire to longitudinal balance, b fle 5 e rx b fle = 20 ? log , e tr source removed v lo 0.2khz < f < 4.0khz 40 db f = 1.0 khz 53 db pbl 3798 tipx ringx rsn vtx r t r rx e rx r lt c e tr r lr v lo 42/27 32/21 43/28 29/19 pbl 3798 tipx ringx rsn vtx r t r rx v tx r lt c r lr v tr e lo 42/27 32/21 43/28 29/19 figure 5. metallic-to-longitudinal (b mle ) and four-wire-to-longitudinal (b fle ) balance. 1/ w c << 150 w , r lt = r lr = 300 w , r t = 60 k w , r rx = 30 k w . figure 4. longitudinal-to-metallic (b lme ) and longitudinal-to-four-wire (b lfe ) balance. 1/ w c << 150 w , r lt = r lr = 300 w , r t = 60 k w , r rx = 30 k w . figure 3. longitudinal input impedance. v lot + v lor z lot = z lor = i lo pbl 3798 tipx ringx v lot c i lo v lor 300 ohms 300 ohms 42/27 43/28 ref parameter fig conditions min typ max unit
4-131 pbl 3798 2-wire return loss, r z l + z tr r = 20 ? log , note 5 z l - z tr 0.2khz f < 0.5khz 30 32 db 0.5khz f < 1.0khz 25 27 db 1.0khz f 3.4khz 15 17 db polarity reversal time, t pol normal to reversed polarity or 4 15 ms reversed to normal polarity tipx idle voltage, v ti normal polarity, stand-by v bat = -48v -5.0 -3.5 -2.0 v v bat = -63v, note 6 -5.0 -3.5 -2.0 v tipx to ringx idle active and standby voltage, v tro v bat = -48v, r l = open loop standard version normal polarity 42 v reversed polarity -42 v -/2 version normal polarity 40 v reversed polarity -40 v 4-wire transmit port (vtx) overload level, v txo 2 load impedance > 20 k w , 3.1 3.5 v pk f = 1 khz, 1% thd, e rx = 0 9.0 10.1 dbu note 7 output offset voltage, d v tx -50 5 +50 mv output impedance, z tx 0.2khz f 3.4khz 10 20 w 4-wire receive port (rsn) rsn dc voltage, v rsn i rsn = 0 -10 0 +10 mv rsn impedance, z rsn 0.2khz f 3.4khz 3 20 ohm rsn current (i rsn ) to metallic 0.2khz f 3.4khz, 40 db loop current (i l ) gain, a rsn i l a rsn = i rsn frequency response two-wire to four-wire, g 2-4 6 0.3khz f 3.4khz -0.1 0.03 +0.1 db relative to 1.0 khz, 0 dbu e rx = 0 v, (notes 2, 8) four-wire to two-wire, g 4-2 6 0.3khz f 3.4khz -0.1 0.03 +0.1 db relative to 1.0 khz, 0 dbu e l = 0 v, (notes 2, 9) four-wire to four-wire, g 4-4 6 0.3khz f 3.4khz -0.1 0.06 +0.1 db relative to 1.0 khz, 0 dbu e l = 0 v, (notes 2, 9) insertion loss two-wire to four-wire, g 2-4 6 0 dbu, 1 khz, e rx = 0 -0.15 0.1 +0.15 db (notes 8, 10) ref parameter fig conditions min typ max unit pbl 3798 tipx ringx rsn vtx r t r rx e rx r l v tr i ldc c e l v tx + + rx tx 42/27 32/21 43/28 29/19 figure 6. frequency response, insertion loss, gain tracking, idle channel noise, thd, inter-modulation. 1/ w c << r l , r l = 600 w , r t = 60 k w , r rx = 30 k w .
4-132 pbl 3798 ref parameter fig conditions min typ max unit four-wire to two-wire, g 4-2 6 0 dbu, 1 khz, e l = 0 -0.15 0.1 +0.15 db (notes 9, 10) four-wire to four-wire, g 4-4 6 0 dbu, 1 khz, e l = 0 -0.15 0.1 +0.15 db (notes 9, 10) gain tracking two-wire to four-wire (note 8) and 6 referenced to -10 dbu, 1 khz four-wire to two-wire (note 9) +3 dbu to -30 dbu -0.1 +0.1 db -30 dbu to -55 dbu 0.1 db noise idle channel noise at two-wire 6 e rx = e l = 0, notes 2, 11 (tipx-ringx) or four-wire (vtx) port c-msg weighting 7 10 dbrnc psophometrical weighting -83 -80 dbup single frequency out-of-band noise (note 12) metallic, v tr 7 12 khz f 1 mhz -58 -55 dbu longitudinal, v lo 7 12 khz f 90 khz -68 -63 dbu longitudinal, v lo 7 90 khz f 1 mhz -53 -50 dbu total harmonic distortion two-wire to four-wire, 6 0.3khz f 3.4khz -64 -50 db four-wire to two-wire 0 dbu, 1 khz test signal, note 2 intermodulation type 2f 1 - f 2 6 0.3 khz < f 1 , f 2 < 3.4 khz, level f 1 = level f 2 = -25 to 0 dbv f 1 1 nf 2 , f 2 1 nf 1 , note 2 two-wire to four-wire e rx = 0 -60 -50 db four-wire to two-wire e l = 0 -60 -50 db type f 1 50 hz 6 0.3khz < f 1 < 3.4khz level 50 hz = level f 1 - 14 db, level f 1 = -15 dbv to 0 dbv f 1 1 n ? 50 hz, note 2 two-wire to four-wire e rx = 0 -65 -50 db battery feed characteristics loop current in constant current 17 r dc1 = r dc2 = 3125 w 38 40 42 ma region, i ldc active state p = 1, active polarity reversal state p = -1 250 i ldc = p ? r dc1 + r dc2 stand-by state p = 1 18 20 22 ma stand-by polarity reversal state p = -1 125 i ldc = p ? r dc1 + r dc2 loop current in constant current 17 r dc1 = r dc2 = 3125 w region at maximum loop resistance, i ldc active state v bat = -48 v, r lmax = 750 w 38 ma v bat = -63 v, r lmax = 1140 w 38 ma pbl 3798 tipx ringx v tr i ldc c + 42/27 43/28 67,5 67,5 56,25 + v ld 20 20 c figure 7. single-frequency out of band noise. resistance values in w , v lo = 1.6 ? v' lo 1/ w c << 100 w
4-133 pbl 3798 figure 9. ring trip comparator. 2v < v < |v bat + 1|, i dt + i dr = i b , 2 v dtr = d v dtr , v' dtr - v dtr d i b = r ref parameter fig conditions min typ max unit loop current outside constant current 17 r dc1 = r dc2 = 3125 w region, |i ldc | active state v bat = -48 v, r lmax = 2 k w 15.5 ma v bat = -63 v, r lmax = 2 k w 23 ma note 13 tip open circuit state tipx current, i ltlkto 8 tip open circuit state -100 5 100 m a v bat < v tto < 0 ringx current, i lrto 8 tip open circuit state r lrgnd = 0 ohm 23 35 50 ma r lrgnd = 2.5 k w , v bat = -63 v 22 24 ma r lrgnd = 2.5 k w , v bat = -48 v 16 18 ma ringx voltage, v rto 8i lrto < 23 ma v bat +1 v bat +4 v bat +14 v loop current detector loop current detector conversion factor i lthoff = k lthoff /r d on-hook to off-hook, k lthoff active, standby, polarity reversal state 395 465 535 v tip open circuit state (note 14) 745 930 1115 v loop current detector conversion factor i lthon = k lthon /r d off-hook to on-hook, k lthon active, standby, polarity reversal state 348 410 472 v tip open circuit state (note 14) 655 820 985 v loop current detector conversion factor active, standby and hysteresis, k lth polarity reversal state (note 15) 20 55 90 v dial pulse distortion 10 pps, off-hook: 600 w 15% on-hook: w ring trip comparator inputs (dt, dr) offset voltage, d v dtr 9v bat + 1 v < v dt , v dr < -2 v r = 0 w -20 10 20 mv r = 200 k w -40 10 40 mv input offset current, d i b 9v bat + 1 v < v dt , v dr < -2 v, r = 200 k w 0.05 1 m a input bias current, i b 9v bat + 1 v < v dt , v dr < -2 v, r = 200 k w 0.1 1 m a i b = (i dt + i dr )/2 input resistance v bat + 1 v < v dt , v dr < -2 v unbalanced, r dt , r dr 1m w balanced, r dtr 3m w common mode range, v dt , v dr v bat +1 -2 v pbl 3798 dt dr det r gnd r v dtr i dt + dtr + v' i dr + v +i dr i dt 38/25 20/13 40/26 pbl 3798 tipx ringx 42/27 43/28 i ltlkto i lrto r lrgnd + v tro figure 8. tip open circuit state.
4-134 pbl 3798 ref parameter fig conditions min typ max unit ground key detector ground key detection threshold, r gnd 10 active & stand-by states, e 0 = e 1 = 1 note 19, 20 switch s1 open 1.7 10.0 k w switch s1 open, r sg 1 1.7 15.0 k w switch s1 closed 0.9 10.0 k w longitudinal current threshold, i logkth 10 s1 closed 8 ma relay driver outputs (ringrly, testrly) on state voltage, v trly , v rrly i trly , i rrly = 25 ma 0 c < t amb < 25 cv cc -2.0 v cc -1.8 v 25 c < t amb < 70 cv cc -1.8 v cc -1.6 v cc -1.0 v off state leakage current, i trly , i rrly v trly , v rrly = v bat 5 100 m a clamp voltage i trly , i rrly = 25 ma v bat -3 v bat -1 v digital inputs (c1-c4, e0, e1, chclk) input low voltage, v il 0.8 v input high voltage, v ih 2.0 v input low current, i il v il = 0.4 v -0.4 ma input high current, i ih v ih = 2.4 v 40 m a digital output (det) output low voltage, v ol i ol = 1.0 ma 0.45 v output high voltage, v oh i oh = -0.1 ma 2.4 v resistive pull-up 12 15 18 k w switch mode regulator transistor output (l) switch transistor saturation voltage, v lsat i l = 100 ma, note 16 1.5 v leakage current, i llk v l = 0 v 200 m a switch mode regulator clock input (chclk) clock frequency, f chclk 253 256 259 khz rise and fall time 50 ns duty cycle ratio 46 54 % power supply rejection ratio (psrr) v cc to two-wire port and saturation guard off v cc to four-wire port 50 hz < f < 4 khz 35 db rejection ratio, psrr cc 4 khz < f < 50 khz 30 db saturation guard on 50 hz < f < 50 khz 20 db note 17 v ee to two-wire port and 50 hz < f < 4 khz 10 db v ee to four-wire port 4 khz < f < 50 khz 0 db rejection ratio, psrr ee note 17 v bat to two-wire port and 50 hz < f < 4 khz 25 db v bat to four-wire port 4 khz < f < 50 khz 20 db rejection ratio, psrr bat note 17 pbl 3798 tipx ringx 42/27 43/28 s1 300 300 r gnd i logkth (s1 closed) figure 10. ground key detector.
4-135 pbl 3798 notes 1. the overload level is specified at the two-wire port with the signal source at the four-wire receive port, i.e. e l = 0 in figure 2. 2. dbm is the ratio between power level p and a 1 mw reference power level, expressed in decibels, i.e. p dbm = 10 ? log 10 1 mw dbu is the ratio between voltage vrms and a 0.775 vrms reference, expressed in decibels, i.e. vrms dbu = 20 ? log 10 0.775 vrms dbu = dbm at impedance level 600 w dbv is the ratio between voltage v and a 1 v reference, expressed in decibels, i.e. v dbv = 20 ? log 10 1 v dbup is the ratio between voltage v p , measured via a psophometrical filter and a 0.775 vrms reference, expressed in decibels, i.e. v p dbup = 20 ? log 10 0.775 vrms dbrnc is the ratio between power level p c , measured via a c-message filter and a 1 pw reference power level, expressed in decibels, i.e. p c dbrnc = 10 ? log 10 1 pw 3. the two-wire impedance, z trx , is programmable by selection of external component values according to: z trx = z t / (g 2-4 ? a ) where: z trx = impedance between the tipx and ringx terminals z t = programming network between the vtx and rsn terminals power supply currents (relay drivers off) v cc supply current, i cc on- or off-hook, active state 8 12 ma v ee supply current, |i ee | on- or off-hook, active state 6 9 ma v bat supply current, |i bat | on-hook, active state 3.5 6 ma power dissipation on-hook total dissipation, p onop v bat = -48 v, open circuit state 60 100 mw on-hook total dissipation, p onsb v bat = -48 v, stand-by state 190 350 mw on-hook total dissipation, p onact v bat = -48 v, active state 225 350 mw off-hook total dissipation, p off68 v bat = -48 v, active state 700 1000 mw r l = 600 w , r dc1 = r dc2 = 3.125 k w note 18 temperature guard junction temperature at threshold, t jg 140 c temperature guard hysteresis, ? t jg 10 c ref parameter fig conditions min typ max unit g 2-4 = tipx-ringx to v ta gain, nom. = 1 (0 db 0.15 db) a = receive current gain, nominally = 100 (40 db 0.15 db) the fuse resistors r f add to the impedance presented by the slic at terminals tipx and ringx for a total two-wire impedance of z tr = z trx + 2r f . 4. normal polarity is defined as the tip lead being at a more positive potential than the ring lead. reversed polarity is defined as the ring lead being at a more positive potential than the tip lead. 5. higher return loss values can be achieved by adding a reactive component to r t , the two-wire terminating impedance programming resistor, e.g. by dividing r t into two equal halves and connecting a capacitor from the common point to ground. for r t = 60 k w the capacitance value is approximately 330 pf. 6. v bat = -64 v is applicable to the pbl 3798 in a 44-pin leaded chip carrier with the rsg terminal connected to the v ee supply. 7. the overload level, v txo , is specified at the four-wire transmit port, vtx, with the signal source at the two-wire port. note that the gain from the two-wire port to the four- wire transmit port is g 2-4 = 1. 8. the level is specified at the two-wire port. 9. the level is specified at the four-wire receive port (rsn). 10. fuse resistors r f1 and r f2 impact the insertion loss as explained in the text, section transmission. the specified insertion loss is for r f1 = r f2 = 0 w . 11. the two-wire idle noise is specified with the port terminated in 600 w (r l ) and with the four-wire receive port grounded (e rx = 0, e l = 0; see figure 6). the four-wire idle noise at vtx is specified with the two- wire port terminated in 600 w (r l ). the four-wire receive port is grounded (e rx = 0, e l = 0; see figure 6). the idle channel noise degrades by approximately 5 db when the saturation guard is active. refer to section battery feed for a description of the saturation guard. 12. these specifications are valid for a longitudinal impedance of 90 w and a metallic impedance of 135 w .
4-136 pbl 3798 pin description plcc: 44 pin and 32-pin, j-leaded chip carrier. dip: 28-pin dual in-line. refer to figure 11. 44plcc 32plcc pdip symbol description 1 nc no internal connection. note 1. 2 1 1 gnd2 ground. no internal connection to gnd1. note 2. 3 2 2 vreg regulated negative voltage for power amplifiers. the switch-mode regulator inductor, filter capacitor and rc stabilization network connect to this pin. 4 3 3 vcc +5 v power supply. 5 nc no internal connection. note 1. 5 tp tp is a thermal conduction pin tied to substrate (v qbat ). note 3. 6 4 4 ringrly ring relay driver output. sources up to 80 ma from vcc. 7 6 5 testrly test relay driver output. sources up to 80 ma from vcc. 8 7 6 l switch-mode regulator drive transistor output. the 1 mh inductor and the catch diode connect to this pin. these components must be connected with shortest possible lead lengths. the catch diode, including connecting leads, must exhibit a low inductance to clamp effectively, when the regulator switch opens. 9 nc no internal connection. note 1. 10 8 7 vbat battery supply voltage. negative with respect to gnd2. 11 9 8 vqbat quiet battery. an external filter capacitor connects between this pin and gnd1 to provide filtered battery supply to signal processing circuits. 12 10 9 chs switch-mode regulator stabilization network input. from this pin a capacitor connects to gnd1 and a series rc network to vreg. 13 nc no internal connection. note 1. 14 11 10 chclk switch-mode regulator ttl compatible clock input. nominal frequency: 256 khz. 15 nc no internal connection. note 1. 16 12 11 c4 c1 , c2 , c3 and c4 are ttl compatible decoder inputs controlling the slic operating states. 17 13 12 e1 detector select input. a logic high level enables the ground key detector. a logic low level enables the loop/ring-trip detector. ttl compatible input. 18 nc no internal connection. note 1. 19 14 e0 detector output enable. a logic high level enables the det output. a logic low level disables the det output. ttl compatible input. the pbl 3798 in dual-in-line package has the det output permanently enabled. 20 15 13 det detector output. inputs c1...c3 and e1 select the detector to be connected to this output. when det is enabled via e0 a logic low level indicates that the selected detector is tripped. the det output is open collector with internal pull-up resistor (15 kohms) to vcc. when disabled, det thus appears to be a resistor connected to v cc . 21 16 14 c2 refer to pin c4 description. 22 17 15 c3 refer to pin c4 description. 23 18 16 c1 refer to pin c4 description. 24 nc no internal connection. note 1 13. refer to section battery feed, case 2. 14. refer to loop monitoring function, loop current detector- active state, loop current detector - tip open state. 15. the loop current detector threshold hysteresis is a function of the r d value. refer to note 14 above. 16. v lsat is the voltage across the saturated transistor, i.e. between terminals vbat and l. 17. power supply rejection ratio test signal is 100 mvrms (sinusoidal). 18. fuse resistor r f1 = r f2 = 0 ohm. 19. r gnd resistance value less than the specified range will trigger the ground key detector, i.e. set the det output to logic level low. 20. if a r sg resistor is used in the 44-pin plcc package, the specification with r sg 1 is applicable.
4-137 pbl 3798 figure 11. pin configuration, 44-pin and 32-pin j-leaded chip carrier and 28-pin dual-in-line package, top view. 44plcc 32plcc pdip symbol description 25 rsg saturation guard programming input. a resistor, r sg , between pins rsg and vee adjusts the saturation guard for operation with v bat from -64 v to -46 v. the pbl 3798 in dual- in-line and 32 pin surface mount package have the saturation guard internally set for operation with v bat = -48 v. 26 19 17 rdc the constant dc loop current is programmed by two resistors connected in series from this pin to the receive summing node (rsn). the resistor junction point is decoupled to gnd1 to filter noise and other disturbances before reaching the rsn input. v rdc polarity is negative for normal tip-ring polarity and positive for reversed tip-ring polarity. |v rdc | = 2.5v in the constant current region. 27 20&21 18 gnd1 ground. no internal connection to gnd2. note 2. 28 nc no internal connection. note 1. 29 22 19 rsn receive summing node. 100 times the current (dc and ac) flowing into this pin equals the metallic (transversal) current flowing between the tipx and ringx terminals. programming networks for constant loop current, 2-wire impedance, and receive gain connect to the receive summing node. 30 nc no internal connection. note 1. 31 23 20 vee -5 v power supply. 32 24 21 vtx transmit vf output. the ac voltage difference between tipx and ringx, the ac metallic voltage, is reproduced as an unbalanced gnd1 referenced signal at vtx with a gain of one. the two-wire impedance programming network connects between vtx and rsn. 33 nc no internal connection. note 1. 34 25 22 hpt tip side (hpt) of ac/dc separation capacitor. 35 26 23 hpr ring side (hpr) of ac/dc separation capacitor. 36 nc no internal connection. note 1. testrly l vbat vqbat chs chclk c4 e1 c2 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ringrly rd hpr hpt vtx vee rsn gnd 1 rdc c 1 c 3 1 2 3 4 5 6 44 43 42 41 40 39 38 37 36 33 35 34 32 31 30 29 nc vcc vreg gnd 2 nc ringx ringx sense tipx tipx sense dr nc dt nc nc nc nc nc nc nc e0 nc rsg nc det 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 tp testrly nc chs chclk c4 e1 tp dt rd hpr hpt vtx vee rsn gnd1 14 15 16 17 18 19 20 4 3 2 1 32 31 30 det e0 c2 c3 c1 rdc gnd1 ringrly vcc vreg gnd2 ringx tipx dr vbat vqbat gnd 2 vreg vcc ringrly testrly l vbat vqbat chs chclk c4 e1 det c2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ringx tipx dr dt rd hpr hpt vtx vee rsn gnd 1 rdc c 1 c 3
4-138 pbl 3798 figure 12. pbl 3798 application example. 44plcc 32plcc pdip symbol description 37 27 24 rd loop current detector programming resistor, r d , connects from rd to vee. a filter capacitor c d may be connected from rd to gnd1. 38 28 25 dt inverting ring trip comparator input. 39 nc no internal connection. note 1. 29 tp tp is a thermal conduction pin tied to substrate (v qbat ). note 3. 40 30 26 dr non-inverting ring trip comparator input. 41 tipx sense tipx sense is internally connected to tipx. tipx sense is used during manufacturing, but requires no connection in slic applications, i.e. leave open. 42 31 27 tipx the tipx pin connects to the tip lead of the 2-wire line interface via overvoltage protection components, ring and test relays. 43 32 28 ringx the ringx pin connects to the ring lead of the 2-wire line interface via overvoltage protection components, ring and test relays. 44 ringx sense ringx sense is internally connected to ringx. ringx sense is used during manufacturing, but requires no connection in slic applications, i.e. leave open. notes 1. pins marked nc are not internally connected. it is recommended to ground these pins to provide shielding for sensitive terminals. 2. the gnd1 and gnd2 pins should be connected together via a direct printed circuit board trace. 3. for 32 pin plcc, these pins (5 and 29) should be connected to v qbat , serving as a heatsink. u1 pbl 3798 subcriber line interface circuit (slic) u2 combination codec/filter u3 secondary protection (e.g. texas instrument tisp pbl 1) note 7. r b resistor 33.2 k w 1% 1 /4 w r fb resistor dependent on application r rx resistor 26.1 k w 1% 1 /4 w r t resistor 51.1 k w 1% 1 /4 w r tx resistor 33.2 k w 1% 1 /4 w r ch resistor 909 w 2% 1 /4 w r 1 , r 3 resistor 200 k w 5% 1 /4 w r 2 resistor 909 k w 5% 1 /4 w r 4 resistor 1.21 m w 5% 1 /4 w r d resistor 51.1 k w 5% 1 /4 w r dc1 , r dc2 resistor 3.09 k w 5% 1 /4 w r sg resistor note 3 5% 1 /4 w r rt resistor 150 w 5% 2 w r bat resistor note 4 r f1 , r f2 resistor 40 w 1% r f1 /r f2 ratio match (e.g. ericsson components pbr 51- series) c bat capacitor0.47 m f 20% 100v c tisp capacitor 220 nf 20% 100v c ch1 capacitor 47 nf 10% 100v c ch2 capacitor1500 pf 10% 100v c d capacitor6200 pf 20% 10v c dc capacitor0.47 m f 10% 10v c flt capacitor0.47 m f 10% 100v c hp capacitor0.33 m f 10% 100v c q capacitor 0.33 m f 20% 100v c rt capacitor 0.39 m f 20% 100v c tc , c rc capacitor 2200 pf10% 100v d 1 diode 100 v100 ma 10 ns (e.g. 1n4448) d 6 diode note 6 d 7 diode 100 v500 ma l inductor 1 mh 10%r 3 15 w (e.g. siemens b78108-s1105-j, j. w. miller 9220-28, nytronics rfc-s, or ericsson reg 522 7103) k t relay, test 4c contacts k r relay, ring 2c contacts notes 1 the ringtrip network may alternatively be located on the ring lead side. the ringtrip network may also be configured for balanced ringing as shown in figure 20. 2 it is recommended to connect pins marked "nc" (44-pin package pins # 1, 5, 9, 13, 15, 18, 24, 28, 30, 33, 36 & 39) to ground. 3. rsg is open circuit for v bat = -48 v and shorted to v ee for v bat = -63 v. for intermediate battery voltages, calculate as described in the section, battery feed, case 2". 4. r bat for one line is recommended to be 5,6 w 5% 1/4w. however the resistor can be shared between several lines, for instance 1 w 5% 1w for eight lines. 5. the ground terminals of the secondary protection should be connected to the common ground on the printed board assembly with a track as short and wide as possible, preferrable a ground plane. 6. for diode type, refer to section "power-up sequence". 7. texas instrument tisp pbl2 should be used when pbl 3798 is programmed for a maximum line current exceeding 60 ma. + 38/25 40/26 42/27 34/22 35/23 43/28 6/4 7/5 10/7 2/1 3/2 8/6 11/8 12/9 dt dr tipx hpt hpr ringx ringrly testrly gnd2 l chs vbat vreg vqbat kr kt 25/- 37/24 31/20 4/3 32/31 29/19 26/17 16/11 22/15 21/14 23/16 20/13 19/- 17/12 14/10 27/18 rsg rd rsn rdc c4 c3 c2 c1 det e0 e1 chclk gnd1 vtx vcc vee -5v +5v 256 khz clock system control interface bat v ringing ring line test channel test tip (90 v rms + v bat ) bat v c ch2 c ch1 c q c flt l c bat c rc c hp c tc c rt c d c dc r dc2 r dc1 r t r b r fb r d r sg r 1 r 4 r 2 r 3 r f1 r rt r f2 r bat d 7 d 1 r ch d 5 k r k r k t k t k t k t low voltage high voltage u 1 u 2 combination codec/filter note 1 v t v rx r rx r tx c tisp bat v k1 k1 k2 k2 a g u 3 note 5 note 2 d 6 vee pbl 3798 nc v ee
4-139 pbl 3798 v tr z t z l g 4-2 == -? v rx z rx z t /100 + 2r f + z l four-wire to four-wire gain the four-wire to four-wire gain, g 4-4 , is derived from (1), (2) and (3) with e l = 0: v tx z t z l + 2r f g 4-4 == -? v rx z rx z t /100 + 2r f + z l hybrid function the pbl 3798 slic forms a particularly flexible and compact line interface when used together with siemens codec filter circuit (sicofi) or other similar program- mable codec/filter. the sicofi allows for system controller adjustment of hybrid balance to accommodate different line impedances without change of hardware. the sicofi also permits the system controller to adjust transmit and receive gains as well as terminating impedance. refer to sicofi or similar programmable codec/filter data sheets for design information. functional description and applications information transmission overview a simplified ac model of the transmission circuits is shown in figure 13. neglecting the impact of the filters in figure 13 for frequencies from 300 hz to 3.4 khz (i.e. filter gain = 1), circuit analysis yields: v tr = v tx + i l ? 2r f (1) v tx v rx i l + = (2) z t z rx 100 v tr = e l - i l ? z l (3) where: v tx is the ground referenced, unity gain version of the ac metallic (transver- sal) voltage between the tipx and ringx terminals, i.e. v tx = 1 ? v trx . v tr is the ac metallic voltage between tip and ring. e l is the line open circuit ac metallic voltage. i l is the ac metallic current. r f is the overvoltage protection current limiting resistor. z l is the line impedance. z t is the programming network for the tipx to ringx impedance. z rx controls the four-wire to two-wire gain. v rx is the analog ground referenced receive signal. from equations (1), (2) and (3) expressions for two-wire impedance, two-wire to four-wire gain, four-wire to two-wire gain and four-wire to four wire gain may be derived. two-wire impedance to calculate z tr , the impedance presented to the 2-wire line by the slic, including the resistors r f , let v rx = 0. from (1) and (2): z t z tr =+ 2r f 100 since z tr and r f are known z t may be calculated from z t = 100 ? (z tr - 2r f ) example: calculate z t to make the terminating impedance z tr = 900 w in series with 2.16 m f. r f = 40 w . using the expression above figure 14. hybrid function. figure 13. simplified ac transmission circuit. a: lowpass filter, -3db @ ? 34 khz b: highpass filter, -3db @ ? 1.8 hz c: lowpass filter, -3db @ ? 1.8 hz * ac-dc separation filter frequency is set by c hp 1 z t = 100 ? (900 + - 2 ? 40) j w ? 2.16 ? 10 -6 1 = 82 ? 10 3 + j w ? 21.6 ? 10 -9 i.e. z t = 82 w in series with 21.6 nf. it is always necessary to have a high ohmic resistor in parallel with the capa- citor. this gives a dc-feedback loop for low frequency which ensure stability and reduces noise. two-wire to four-wire gain the two-wire to four-wire gain, g 2-4 , can be obtained from (1) and (2) with v rx = 0: v tx z t /100 g 2-4 == v tr z t /100+2r f four-wire to two-wire gain the four-wire to two-wire gain, g 4-2 , is derived from (1), (2) and (3) with e l = 0: tipx ringx ring tip 1 -1/20 1 -1/5 rdc rsn vtx r dc2 r dc1 z t z rx v tx v rx c dc r f r f -i l /500 -i l /500 -i l -i l v trx v tr z tr z l e l + + a b* c a pbl 3798 + i l /100 + + x 500 x 500 42/27 43/28 26/17 29/19 32/21 combination codec/filter - + pbl 3798 z t z rx z b r tx r fb rsn vtx v t v rx 32/21 29/19
4-140 pbl 3798 balance network, z b . basic algebra yields: r l r b1 = r tx ? = 25.2 k w r l + 2r f 2r f r b = r tx ? = 2237 w r l + 2r f (r l + 2r f ) 2 ? c l c b = = 0.95 m f r tx ? 2r f longitudinal impedance a feedback loop counteracts longitudinal voltages at the two-wire port by injecting longitudinal currents in opposing phase. therefore longitudinal disturbances will appear as longitudinal currents and the tipx and ringx terminals will experien- ce very small longitudinal voltage excursions well within the slic common mode range. this is accomplished by comparing the instantaneous two-wire longitudinal voltage to an internal reference voltage, v loref . as shown below, the slic appears as 20 w to ground per wire to longitudinal disturbances. it should be noted, that longitudinal currents may exceed the dc loop current without disturbing the vf transmission. from figure 15 the longitudinal impedance can be calculated: v lo r lo = = 20 w i lo 100 where: v lo is the longitudinal voltage i lo is the longitudinal current r lo = 2 k w sets the longitudinal impedance capacitors c tc and c rc the capacitors designated c tc and c rc in figure 12, connected between tipx and ground as well as between ringx and ground, are recommended as an addition to the overvoltage protection network. very fast transients, appearing on tip and ring, may pass by the overvoltage pro-tection network, before this device has had time to activate and could damage the slic. c tc and c rc short such very fast transients to ground. the recommended value for c tc and c rc is 2200 pf. higher capacitance values may be used, but care must be taken to prevent degradation of either longitudinal balance or return loss. c tc and c rc contribute a metallic impedance of 1/( p f c tc ) ? 1/( p f c rc ), a tipx to ground impedance of 1/(2 p f c tc ) v rx z b = - r tx ?= v tx z rx z t /100 + 2r f + z l = r tx ?? z t z l + 2r f example: z tr = z l = 900 w (r l ) in series with 2.16 m f (c l ) r f = 40 w , r tx = 27.4 k w , g 4-2 = -1. calculate z b . using the z b formula above: z rx 2z l z b = {z l = z tr } = r tx ? ? = z t z l + 2r f z l = {g 4-2 = -1} = r tx ?= z l + 2r f 1 + j w ? r l ? c l = r tx ? 1 + j w ? (r l + 2r f ) ? c l a network consisting of r b1 in series with the parallel combination of r b and c b has the same form as the required the hybrid function in an implementa- tion utilizing the uncommitted amplifier in a conventional codec/filter combina- tion is shown in figure 14. via impedance z b a current proportional to v rx is injected into the summing node of the combination codec/filter amplifier. as can be seen from the expression for the four-wire to four-wire gain a voltage proportional to v rx is returned at vtx. this voltage is converted by r tx to a current flowing into the same summing node. these currents can be made to cancel each other by letting: v tx v rx += 0 (e l = 0) r tx z b substituting the four-wire to four-wire gain expression, g 4-4 , for v rx /v tx yields the formula for the balance network: figure 15. longitudinal feedback loop. v loref = (v tip + v ring )/2 (without any longitudinal voltage component). figure 16. battery feed. + - pbl 3798 1 1 r r r hp /2 r hp /2 r lo = 2 kohms v lo v loref v lo + v loref i lo /100 i lo c hp ringx hpr hpt tipx i lo i lo v lo v lo i lo 1 42/27 34/22 35/23 43/28 +1 normal -1 reversed p -2.5 v i ldc /100 rsn rdc v reg (normal) gnd2 (reversed polarity) v reg (reversed polarity) gnd2 (normal) v trdc v trxdc + + tip ring r f r f ringx tipx PBL3798 r dc2 r dc1 c dc i ldc i ldc 42/27 43/28 29/19 26/17
4-141 pbl 3798 limiting the short circuit loop current to 50% of the active state short circuit current. the following paragraphs describe the battery feed circuit in detail. at the end of this section a paragraph, battery feed circuit programming procedure, summa- rizes the few simple calculations necessary to program the battery feed. case 1: slic in the active or active polarity reversal state; |v trdc | < v sgref , |v bat | > v sgref + 12 v in the active state c3, c2, c1 = 0, 1, 0 and in the active polarity reversal state c3, c2, c1 = 1, 1, 0. the battery feed control loop is shown in block diagram form in figure 16. for tip to ring dc voltages less than the satura- tion guard reference voltage, v sgref (refer to case 2) the following expression is obtained from the block diagram for r f =0. 250 i ldc = p ? r dc1 + r dc2 where: i ldc is the constant dc loop current r dc1 , r dc2 are the external constant current programming resistors p = 1 for normal polarity, -1 for reversed polarity in figure 17, curve segment ab (dip 32 pin or 44 pin plcc or ac 44 pin plcc is described by case 1. case 2: slic in the active or active polarity reversal state; |v trdc | > v sgref , |v bat | > v trdc +12v in the active state c3, c2, c1 = 0, 1, 0 and in the active polarity reversal state and a ringx to ground impedance of 1/(2 p f c rc ). ac - dc separation capacitor the high pass filter capacitor connected between terminals hpt and hpr provides separation between circuits sensing tipx-ringx dc conditions and circuits processing vf signals. the recommended c hp capacitance value of 220 nf will position the 3 db break point at 1.8 hz. battery feed overview the pbl 3798 slic synthesizes a constant current feed system without the disadvantage of high feed circuit power dissipation on short loops. to reduce power dissipation a switch mode regulator efficiently down-converts the battery supply voltage. the down- converted voltage is applied to the line drive amplifiers and is automatically adjusted to be precisely enough to feed the loop current as well as to allow distortion free vf signal transmission. the magnitude of the constant loop current is set by two external resistors. the battery feed polarity can be set to either normal or reversed polarity via the slic digital control inputs. to permit the line drive amplifiers to operate without signal distortion even on high resistance or open circuit loops, a saturation guard circuit limits the loop voltage, when the tip to ring dc voltage approaches the available battery supply voltage. with the slic set to the stand-by state, power is further conserved by figur 17. pbl 3798 battery feed r dc1 =r dc2 =3,125 k w , i ldc =40ma. curve abe: active state. pbl 3798 in 28-pin dip, 32 pin or 44-pin plcc with r sg = w and v bat = -48v. curve acd: active state. pbl 3798 in 44-pin plcc with r sg = 0 w and v bat = -63v. curve fgj: stand-by state. pbl 3798 in 28-pin dip, 32-pin or 44-pin plcc with r sg = w and v bat = -48v. curve fhi: stand-by state. pbl 3798 in 44-pin plcc with r sg = 0 w and v bat = -63v. c3, c2, c1 = 1, 1, 0. when the tip to ring dc voltage approaches the v bat supply voltage, a circuit named saturation guard limits the two wire voltage to a small additional increase beyond the saturation guard threshold, v sgref . this is to maintain distortion free vf transmission through the line drive amplifiers. the saturation guard feature makes on-hook transmis- sion possible. the tip to ring voltage at which the saturation guard becomes active, v sgref , can be calculated from where v sgref is in volts for r sg in k w . r sg is a resistor connected between terminal rsg and -5v. note that the rsg terminal is availible only on the 44-pin surface mount package. the 28-pin dual-in- line and 32-pin surface mount package have the saturation guard internally set to v sgref = 34.1v. r sg = open circuit yields v sgref = 34.1v. r sg = 0 w yields v sgref = 48.6v. the loop current, i ldc , as a function of the loop voltage, v trdc , for v trdc > v sgref is described by the open circuit voltage is then, for a programmed loop current of 40ma, 38.9v for r sg = open circuit and 53.4v for r sg = 0 w . 40 50 30 20 10 20 40 60 v trdc [ v ] not acceptable not acceptable not acceptable a b c h d f g j 10 e i 30 50 70 0 0 [ ma ] i l v sgre f = 34,1 0,676 1- r sg + 2,26 v sgre f - v trdc 250 120 r dc1 + r dc2 i ldc = +
4-142 pbl 3798 switch mode regulator the switch mode regulator down- converts the v bat supply voltage to a value, which is just enough for the line drive amplifiers to feed the required loop current and maintain transmission quality. since the voltage conversion efficiency is high and the minimum required voltage drop across the line drive amplifiers is low, a significant power dissipation reduction is realized. a 50 ma constant current feed with 200 w line resistance and -48 v battery will have 1.9 w dissipated in the line feed circuit. the pbl 3798 set up for the same 50 ma constant current feed and with the same 200 w line resistance and v bat = -48 v, would generate only 0.72 w in the line feed circuits (90% power conversion efficiency), i.e. a 1.18 w or 62.1% reduction in line card power dissipation. refer to figure 18 for a block diagram of the switch mode regulator. v bat is the input voltage, which the regulator converts to v reg with high efficiency. v reg powers the line drive amplifiers. the switch mode regulator adjusts its v reg output to be equal to the reference voltage, v ref . the reference voltage is derived from the tipx to ringx dc metallic voltage according to v ref = -(|v trdc | + v bias ) where v bias is approximately 12 v. since v bias is the voltage drop across the line drive amplifiers, the slic power loss is greatly reduced compared to supplying the amplifiers directly from the v bat supply. the battery supply voltage, |v bat |, must be larger than |v reg |, i.e. |v bat | 3 |v trdc | + v bias . if this condition is not met, the tip to ring voltage will be limited by the slic according to |v trdc | = |v bat | - v bias . although the slic continues to function, this mode of operation should be avoided due to increased noise and a much reduced v bat to transmission ports rejection ratio. to minimize noise as well as battery feed circuit power dissipation on long loops the switch mode regulator is automatically turned off for tip to ring dc voltages exceeding a threshold value of approximately v sgref - 1v. with the regulator disabled, the v bat supply voltage is passed on to the vreg input without being down-converted. case 5: slic in the tipx open circuit state. in the tipx open circuit state c3, c2, c1 = 1, 0, 0. refer to figure 8. in this state the tipx terminal is set to a high- impe-dance state (> 150 k w ). the ringx terminal sinks a current (|i lrto | > 23 ma until the v bat voltage is approached, whereafter the ringx terminal changes to a constant voltage state and the ringx current can be calculated from: |v bat + 4| |i lrto | = r lrgnd where; r lrgnd is the resistor between ground and ring lead. c dc capacitor refer to the battery feed block diagram, figure 16. the battery feed programming resistors r dc1 and r dc2 together with capacitor c dc form a low pass filter, which removes noise and vf signals from the battery feed control loop. the recommended 3 db break point frequency is 160 hz < f 3db < 240 hz. the c dc capacitance value is then calculated from: 1 11 c dc =?+ 2 p ? f 3db ? r dc1 r dc2 ? note that r dc1 = r dc2 yields minimum c dc capacitance value. figure 18. switch mode regulator. in figure 17, pbl 3798 battery feed examples, curve segment cd and be are described by case 2. case 3: slic in the stand-by or stand- by polarity reversal state; |v trdc | < v sgref , |v bat | > v sgref + 12 v the stand-by operating states reduce power dissipation. the loop feed in the stand-by state (c3, c2, c1 = 0, 1, 1) and in the stand- by polarity reversal state (c3, c2, c1 = 1, 1, 1) is constant current according to: 125 i ldc = p ? r dc1 + r dc2 in figure 17, pbl 3798 battery feed examples, this corresponds to curve segments fg and fh. case 4: slic in the stand-by or stand-by polarity reversal state; |v trdc | > v sgref , |v bat | > v sgref + 12v in the stand-by state c3, c2, c1 = 0, 1, 1 and in the stand-by polarity reversal state c3, c2, c1 = 1, 1, 1. when the tip to ring dc voltage exceeds the saturation guard reference voltage, v sgref , the loop feed is described by in figure 17, this corresponds to curve segments hi and gj. pbl 3798 gnd2 v reg v ref gnd2 switch control 2/1 3/2 8/6 10/7 11/18 12/9 14/10 v qbat v qbat chs c ch2 c ch1 r ch c bat l l d 1 v reg c flt chclk (256 khz) i ldc = + v sgre f - v trdc 125 120 r dc1 + r dc2
4-143 pbl 3798 the inductor, l, should be 1 mh with a series resistance larger than 15 w . a saturated inductor with less than 15 w of series resistance may damage the slic due to excessive regulator switch current. c flt , 0.47 m f, is the regulator output filter capacitor. the catch diode, d 1 , (e.g.1n4448) must withstand 70 v reverse voltage, conduct an average of 50 ma (150 ma peak) and turn off in less than 10 nsec. c ch1 , c ch2 and r ch make up a com- pensation network for an internal voltage comparator. values are given in the applications example, figure 12. the components associated with the switching regulator must be connected via the shortest possible pcb trace lengths. other circuits should be kept isolated from this area. the l terminal voltage variations are large and very fast. to avoid interference the inductor and the catch diode should be located directly at this terminal. inductors with closed magnetic path core (e.g. toroid, pot core) will reduce interference originating from the inductor. battery feed circuit programming procedure extracting the key elements from the preceeding description results in the following step-by-step procedure. 1. establish the battery feed require- ments. constant loop current, i ldc = ? maximum loop resistance, including fuse resistors r f1 and r f2 , r lmax = ? loop resistance, above which it is permissible for the loop feed to change from constant current feed to resistive feed, r lsgref = ? loop current at the maximum loop resistance (applies if i ldc ? r lmax > v sgref ) i lmin = ? slic supply voltage, v bat = ? 2. calculate the constant current programming components r dc1 and r dc2 from 250 1 r dc1 = r dc2 =? i ldc 2 3. calculate c dc from 1 11 c dc =?+ 2 p ? f 3db ? r dc1 r dc2 ? where f 3db ? 200 hz loop monitoring functions overview the pbl 3798 slic contains three detectors: the loop current, the ground key and the ring trip detector. these three detectors report their status via the shared det output. the detector to be connected to the det output is selected according to the logic states at the control inputs c1, c2, c3 and enable input e1. enable input e0 (available only on the 32 pin and 44-pin surface mount packages) sets the det output to either active or high impedance state. loop current detector - active state and standby state active state (c3, c2, c1 = 0, 1, 0) and active polarity reversal state (c3, c2, c1 = 1, 1, 0) as well as standby state (c3,c2, c1 = 0, 1,1) and standby polarity reversal state (c3, c2, c1 = 1, 1, 1). the loop current value at which the loop current detector changes state is programmable by calculating a value for resistor r d . r d connects between terminals rd and vee. figure 19 shows a block diagram for the loop current detector. the two-wire interface produces a current, i rd , flowing out of pin rd: |i lt - i lr ||i l | i rd = 0.5 ? = 300 300 where i lt and i lr are currents flowing into the tipx and ringx terminals and i l is the loop current. the voltage generated across the programming resistor r d by i rd is applied to an internal comparator with hysteresis. the comparator reference voltage for transition on-hook to off-hook is 1.55 v. the reference voltage for a transition off-hook to on- hook is 1.37 v. a logic low level results at the det output, when the comparator reference voltage is exceeded. for a specified on-hook to off-hook loop current threshold, i lthoff , r d is calculated from 1.55 ? 300 r d = |i lthoff | the calculated r d value corresponds to an off-hook to on-hook loop current threshold, i lthon , of 1.37 ? 300 |i lthon | = r d 4. calculate the saturation guard programming resistor, r sg . pbl 3798 in 28-pin dual-in-line and 32-pin surface mount package: no rsg terminal provided. v sgref is internally set to 34.1v. the mini- mum required battery voltage is |v batmin | = v sgref +12 v. for loop voltages greater than v sgref , |v batmin | = v trdc +12 v. pbl 3798 in 44-pin surface mount package: rsg terminal open circuit: v sgref = 34.1v. r sg terminal shorted to v ee : v sgref = 48.6v. for intermediate v sgref values calculate r sg according to where r sg is in k w for v sgref in volts. the minimum required battery voltage is |v batmin | = v sgref +12 v. for loop voltages greater than v sgref , |v batmin | = v trdc +12 v. 5. calculate the loop resistance at which the saturation guard becomes active, r lsgref : v sgref r lsgref = i ldc confirm compatibility with require- ments. 6. if i ldc ? r lmax > v sgref , calculate loop current at maximum loop resistance: confirm compatibility with requirements. 7. recommended switch mode regulator component values: l = 1 mh 10 %; c flt = 0.47 m f 10%, 100 v; d 1 = 1n4448 (or equivalent), r ch = 909 w 2%, 0.25 w; c ch1 = 0.047 m f 10%, 100 v; c ch2 = 1500 pf 10%, 100 v. r sg = - 1,59 14,5 1+ v sgre f - 48,6 i ldc min = 250 v sgre f + 120 ? r dc1 + r dc2 120 + r lmax
4-144 pbl 3798 ground key detector refer to figure 19 for a block diagram of the ground key detector. the ground key detector examines the difference between tipx and ringx currents. when the longitudinal current from ground exceeds an internally set threshold value of nominally 8 ma, the detector triggers and where f 3db = 500 hz is the high end frequency response 3db break point for the low pass filter created. c d is in farads for r d in w . note that c d may not be required if the detector output is software filtered. loop current detector - tip open circuit state tip open circuit state (c3, c2, c1 = 1, 0, 0) in the tip open circuit state the loop current detector function is similar to the active state, but the rd terminal current, i rd , is calculated from i lr i rd = where i lr is the ring lead current. 600 the detector is triggered at a ring lead threshold current i lrthoffto with the r d resistance value set to 1.55 ? 600 r d = i lrthoffto the ring lead current must be reduced to less than 1.37 ? 600 i lrthonto = r d for the detector to return to its non- triggered state. loop current detector - filter capacitor figure 19. loop current and ground key detector. figure 20. ring trip network, balanced ringing. 2-wire interface input decoder pbl 3798 + - rd vee r d d -5v |i lt - i lr | 2 ?300 ringx tipx i lt i lr c1 c2 e0 det v cc c3 mux b v cref ring trip comparator loop current comparator c b a (i lt -i lr ) 1000 + - gnd key comparator r h 42/27 43/28 37/24 31/20 mux a loop current or gnd key 17/12 19/ 20/13 22/15 21/14 23/16 ring/trip comp + tipx ringx dt dr c1 c2 c3 det e0 mux b input decoder e batr e r e r+ r b2 r b1 r 3 r 4 r 2 r 1 r f r f k r k r rt1 c rt2 c tip ring subscriber line pbl 3798 v cc mux a e1 gnd key derector 38/25 40/26 42/27 43/28 23/16 21/14 22/15 20/13 19/ 17/12 to increase the loop current detector noise immunity, a filter capacitor may be added from terminal rd to ground. a suggested value for c d is: 1 c d = 2 p ? r d ? f 3db
4-145 pbl 3798 lead or the ring lead with return on the other wire. a ring relay, energized by the slic ring relay driver, connects the ringing source to tip and ring. for unbalanced ringing systems the loop current sensing resistor may be placed either in series with the ringing generator or in series with the return lead to ground. figures 20 and 21 show examples of balanced and unbalanced ringing systems. for either ringing system the ringtrip detection function is based on a polarity change at the inputs dt and dr of the ringtrip comparator. in the unbalanced case the dc voltage drop across resistor r rt is zero as long as the telephone remains on-hook. with the telephone off-hook during ringing, dc loop current will flow, causing a voltage drop across r rt . the r rt voltage is applied to the comparator input dt via resistor r 3 . r 4 shifts the voltage level to be within the comparator common mode range. c rt removes the ac component of the ringing signal. r 1 and r 2 establish a bias voltage at comparator input dr, which is more negative than dt when the telephone is on-hook and is more positive than dt when the telephone goes off-hook during ringing. complete removal of the ringing signal ac component at the dt input may not be necessary. some residual ac component at the dt input may under certain operating conditions cause the det output to toggle between the on- hook and off-hook states at the ringing sets the det output to a logic low level. the e1 enable input must be set to logic high level to gate the ground key detector to the det output. the electrical characteristics table specifies the threshold level as a function of longitudinal resistance to ground. the ground key detector threshold is pre-programmed and cannot be changed by external components. ring trip detector ring trip detection is accomplished by monitoring the two-wire line for presence of dc current while ringing is applied. when the subscriber goes off-hook with ringing applied, dc loop current starts to flow. the comparator in the slic with inputs dt and dr detects this current flow via an interface network. the result of the comparison is presented at the det output. the ring trip comparator is automatically connected to the det output, when the slic control inputs are set to the ringing state (c3, c2, c1 = 0, 0, 1). when off-hook during ringing is detected, the line card or system controller will proceed to disconnect the ringing source (software ringtrip) by re- setting the control input logic states. alternatively, the det output may be monitored by circuits on the line card, which perform the ringtrip function (hardware ringtrip). the ringing source may be balanced or unbalanced, superimposed on the v bat supply voltage. the unbalanced ringing source may be applied to either the tip figure 21. ring trip network, unbalanced ringing. frequency. however, with the telephone off-hook the det output will be at logic low level for more than half the time. therefore, by sampling the det output, a software routine can discriminate between on-hook and off-hook through examination of the duty cycle. full removal of the ringing frequency from the dt input while maintaining ringtrip within required time limits (approximately < 100 ms) usually mandates a second order filter rather than the first order shown in figure 21. the software approach minimizes the number of line card components. in the balanced ringing system shown in figure 20, r 1 and r 2 are the loop current sensing resistors. with the telephone on-hook, no dc loop current flows to cause a dc voltage drop across resistors r 1 and r 2 . voltage dividers r b2 , r 4 and r b1 , r 3 bias the ringtrip compara- tor input dt to be more positive than dr. with the telephone off-hook during ringing dc loop current will flow, causing a voltage drop across resistors r 1 and r 2 , which in turn will make comparator input dt more negative than dr, setting the det output to logic low level, indicating ringtrip condition. capacitors c rt1 and c rt2 filter the ring voltage at the comparator inputs. for 20 hz ringing it is suitable to calculate these capacitors for a time constant of t = 50 ms, i. e. ( 1 1 ) c rt1 = t ? + r b2 r 4 pbl 3798 dr dt r 1 r 2 r 4 r 3 r rt c rt e rg v bat ring tip k r + - subscriber line ring trip comparator 38/25 40/26
4-146 pbl 3798 control inputs overview the pbl 3798 slic has four ttl compatible control inputs, c1 through c4. a decoder in the slic interprets the control input logic conditions and sets up the commanded operating state. c1 through c3 allow for eight operating states. the c4 control input acts directly on the test relay driver. the control inputs interface with programmable codec/filters, e.g. slac, sicofi, combo ii without any interface components. via serial i/o ports on the programmable codec/ filter devices a microprocessor can communicate with the slic. in designs utilizing conventional codec/filters without control latches, the line card logic must contain the neccessary latches for inputs c1 through c4. table 1 contains a summary descrip- tion of the control inputs. test relay control (c4) with c4 set to logic low level the test relay driver (testrly) is activated. the active driver can source up to 80 ma from the v cc supply. c4 set to logic high level causes the relay driver to be de- energized. the test relay driver is controlled exclusively by c4 and is independent of the c1, c2 and c3 logic levels. open circuit state (c3, c2, c1 = 0, 0, 0) in the open circuit state both the tipx and ringx power amplifiers present a high impedance to the line. the loop current and ground key detectors are not active in this state. ringing state (c3, c2, c1 = 0, 0, 1) the ring relay driver (ringrly) is activated and the ring trip comparator is connected to the detector output (det). the tipx and ringx terminals are in the high impedance state and signal transmission is inhibited. active state (c3, c2, c1 = 0, 1, 0) tipx is the terminal closest to ground potential and sources loop current, while ringx is the more negative terminal and sinks loop current. signal transmission is normal and the loop current or ground key detector is gated to the det output according to enable input e1 logic state. c4 c3 c2 c1 operating state active detector state # note 1 note 2 1 x 0 0 0 open circuit ring trip comparator 2 x 0 0 1 ringing ring trip comparator 3 x 0 1 0 active loop current or ground key 4 x 0 1 1 stand-by loop current or ground key 5 x 1 0 0 tip open loop current, note 3 6 x 1 0 1 reserved none 7 x 1 1 0 active polarity reversal loop current or ground key 8 x 1 1 1 stand-by polarity reversal loop current or ground key notes 1. control input c4 logic state (x) affects only the test relay driver and does not change the slic operating state. c4 at logic low level activates the test relay driver. c4 at logic high level turns the test relay driver off. 2. enable input e1 must be set to select between loop current and ground key detector. 3. the ground key detector is not functional in the tip open circuit state table 1. pbl 3798 operating states. table 2. enable inputs e0 and e1. enable e0 e1 det output state active detector state # note 1 1 0 x high impedance none 2 1 0 active loop current or ringtrip. note 2 3 1 1 active ground key notes 1. enable input e0 is available only on the 32 pin and 44-pin surface mount package option. in the 28 pin dual-in-line package the det output is set to active state. 2. the loop current detector or the ring trip comparator is selected via c3, c2, c1 (state# 2 selects the ringtrip comparator. detector output, det the loop current detector, ground key detector and ringtrip comparator share a common output, det. the det output is open collector with internal pull-up resistor to v cc . via control inputs c1 through c3 and enable input e1 one of the three detectors is selected to be connected to the det output. with enable input e0 set to logic high level the det output is activated. in the det active state a logic low level indicates a triggered detector condition and a logic high level reports a non-triggered detector. with e0 set to logic low level, the det output is set to its high impedance state, i.e. connected to v cc via the internal pull-up resistor. note that the det high impedance state is available only on the 32-pin and 44-pin surface mount package. relay drivers the pbl 3798 slic contains two identical drivers for test and ring relays. the drivers are pnp transistors in open collector configuration, sourcing up to 80 ma from the v cc supply. each driver has an internal inductive kick-back clamp diode. the relay coil may be connected to negative supply voltages ranging from ground to v bat . control input c4 activates the test relay driver. control inputs c1, c2 and c3 are used to operate the ring relay.
4-147 pbl 3798 detector when at logic high level. table 2 summarizes the above description of the enable inputs. overvoltage protection the pbl 3798 slic must be protected against overvoltages on the telephone line caused by lightning, ac power contact and induction. refer to maxi- mum ratings, tipx and ringx termin- als, for maximum allowable continuous and transient voltages that may be applied to the slic. the circuit shown in figure 12 utilizes series resistors together with a pro-grammable overvoltage protector (e g texas instrument tisp pbl 1), serving as a secondary protection. the protector network in figure 12 is designed to meet requirements in itu-t k20, table 1. the tisp pbl 1 is a dual forward- conducting buffered p-gate overvoltage protector. the protector gate references the protection (clamping) voltage to negative supply voltage (i e the battery voltage,v bat ). as the protection voltage will track the negative supply voltage the overvoltage stress on the slic is minimized. positive overvoltages are clamped to ground by an internal diode. negative overvoltages are initially clamped close to the slic negative supply rail voltage. if sufficient current is available from the overvoltage, then the protector will crowbar into a low voltage on-state condition, clamping the overvoltage close to ground. a gate decoupling capacitor, c tisp is needed to carry enough charge to supply a high enough current to quickly turn on the thyristor in the protector. without the capacitor even the low inductance in the track to the v bat supply will limit the current and delay the activation of the thyristor clamp. the fuse resistors r f serve the dual pur- poses of being non- destructive energy dissipators, when transients are clamped and of being fuses, when the line is exposed to a power cross. ericsson components ab offers a series of thick film resistors networks (e g pbr 51- series and pbr 53-series) designed for this application. also devices with a built in resetable fuse function is offered (e g pbr 52- series) including positive temperature coefficient (ptc) resistors, working as stand-by state (c3, c2, c1 = 0, 1, 1) in the stand-by state the short circuit loop current is reduced to: i ldc = 125 / (r dc1 + r dc2 ). the loop current or ground key detector is connected to the det output in accordance with the e1 input logic state. tipx open circuit state (c3, c2, c1 = 1, 0, 0) the tipx power amplifier presents a high impedance to the line. the ringx terminal is active and sinks current. the loop current detector is connected to the det output for enable input e1 = 0. the detection threshold for the on-hook to off-hook transition is i lrthoffto = (1.55 ? 600) / r d . for e1 = 1 the ground key detector is connected to the det output. note that the ground key detector is not functional in the tip open circuit state. reserved state (c3, c2, c1 = 1, 0, 1) this state has no assigned function. active polarity reversal state (c3, c2, c1 = 1, 1, 0) tipx and ringx polarity is reversed from the active state: ringx is the terminal closest to ground and sources loop current while tipx is the more negative terminal and sinks current. polarity reversal transition time is 4 msec. the loop current or ground key detector is connected to the det output in accordance with the e1 input logic state. signal transmission is normal. stand-by polarity reversal state (c3, c2, c1 = 1, 1, 1) polarity reversal as described under state c3, c2, c1 = 1, 1, 0 and stand-by as described under state c3, c2, c1 = 0, 1, 1. enable inputs the 44-pin and 32-pin surface mount package version of the pbl 3798 slic has two ttl compatible enable inputs, e0 and e1. the 28 pin dual-in-line package version of the pbl 3798 has one enable input, e1. e0 sets the det output to active state, when at logic high level and to high impedance state when at logic low level. e1 selects the loop current detector to be gated to the det output, when at logic low level and the ground key resetable fuses, in series with thick film resistors. note that it is important to always use ptcs in series with resistors not sensitive to temperature, as the ptc will act as a capacitance for fast transients and therefore the ability to protect the slic will be reduced. if there is a risk overvoltages on the v bat terminal on the slic, then this terminal should also be protected. over-temperature protection a ring lead to ground short circuit fault condition, as well as other improper operating modes, may cause excessive slic power dissipation. if junction temperature increases beyond 140 c, the temperature guard will trigger, causing the slic to be set to a high impedance state. in this high impedance state power dissipation is reduced and the junction temperature will return to a safe value. once below 130 c junction temperature the slic is returned back to its normal operating mode and will remain in that state assuming the fault condition has been removed. power-up sequence the voltage at pin vbat sets the sub- strate voltagev qbat (supplied internally from v bat through a resistor), which must at all times be kept more negative than the voltage at any other terminal. this is to maintain correct junction isolation between devices on the chip. to prevent possible latch-up, the optimal power-up sequence is to connect ground and v bat , then other supply voltages and signal leads. should the v bat supply voltage be absent or if vee or vcc must for other reasons be connected before vbat, a diode with low forward voltage drop (schottky diode or a diode with a 1 a current rating) connected with its cathode to vee and anode to vqbat, ensures the presence of the most negative supply voltage at the vqbat pin. the v bat voltage should not be applied at a faster rate than dv bat /dt = 4 v/ m sec, e.g. a time constant formed by a 5.1 w resistor in series with the vbat pin and a 0.47 microfarad capacitor from the vbat pin to ground. one resistor may be shared by several slics.
4-148 pbl 3798 printed circuit board layout care in pcb layout is essential for proper function. the components connecting to the rsn input should be placed in close proximity to that pin, such that no interference is injected into the rsn terminal. a ground plane surrounding the rsn pin is advisable. the c hp capacitor should be placed close to terminals hpt and hpr to avoid unwanted disturbances. the switch mode regulator compo- nents must be located near the pins to which they connect. it is particularly important that the catch diode and the inductor are connected via shortest possible trace lengths. ground terminals gnd1 and gnd2 should be connected via a direct pcb trace at the device location. ordering information package temp. range part no. plastic dip 0 to 70 c pbl 3798n plcc 44 pin 0 to 70 c pbl 3798qn plcc 32 pin 0 to 70 c pbl 3798rn plcc 44 pin 0 to 70 c pbl 3798/2qn plcc 32 pin 0 to 70 c pbl 3798/2rn specifications subject to change without notice. 1522-pbl 3798 uen rev. a ? ericsson components ab, april 1997 this product is an original ericsson product protected by us, european and other patents. ericsson components ab s-164 81 kista-stockholm, sweden telephone: (08) 757 50 00 information given in this data sheet is believed to be accurate and reliable. however no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of ericsson components ab. these products are sold only according to ericsson components ab' general conditions of sale, unless otherwise confirmed in writing.

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